SFP 40G 1310nm Dual LC DDM

Features

ü  Supports 41.2Gbps aggregate bit rates

ü  Uncooled 4x10.3Gbps CWDM transmitter

ü  High-sensitivity PIN-TIA receiver

ü  Up to 10km on SMF

ü  Duplex LC receptacles

ü  Hot pluggable QSFP+ form factor

ü  Power dissipation < 3.5W                    

ü  All-metal housing for superior EMI performance

ü  RoHS6 compliant (lead free)

ü  Operating case temperature:

Commercial: 0ºC to +70°C    

Applications

ü  40GBASE-LR4

ü  InfiniBand QDR and DDR interconnects

ü  40G Telecom connections

ü

Standards

ü  Compliant with SFF-8436

ü  Compliant with SFF-8636

ü  Compatible with IEEE802.3ba

Description

The QSFP+ transceivers are designed for use in 40-Gigabit Ethernet links up to 10km over Single Mode Fiber.

The transceivers are compatible with SFF-8436 and SFF-8636. For further information, please refer to SFF-8436 and SFF-8636.

 Module Block Diagram

Absolute Maximum Ratings

Recommended Operating Environment

Electrical Characteristics

Notes:

1.    Connected directly to TX data input pins. AC coupling from pins into laser driver IC.

Optical Parameters

 Notes:

1. The optical power is launched into 9/125µm SMF.

2. Measured with a PRBS 2³¹-1 test pattern @10.3125Gbps.

3. Measured with a PRBS 2³¹-1 test pattern @10.3125Gbps, ER=4dB, BER <10^-12.

Pin Definitions

Pin Descriptions

Notes:

Plug Seq.: Pin engagement sequence during hot plugging.

1. Module ground pins GND are isolated from the module case.

2. VccRx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently.

Recommended Power Interface Circuit

Recommended Interface Circuit

Digital Diagnostic Functions     

The QSFP+ transceivers support the 2-wire serial communication protocol as defined in the QSFP+ MSA, which allows real-time access to the following operating parameters: 

ü  Transceiver temperature 

ü  Laser bias current 

ü  Transmitted optical power

ü  Received optical power

ü  Transceiver supply voltage 

It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range. 

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed.  For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0 and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.

Ordering information

References

1. SFF-8436 Specification for QSFP+ Copper and Optical Transceiver, Rev 4.7, February 2013.

2. SFF-8636 Specification for Management Interface for Cabled Environments, Rev 2.6, June 2015.

3. IEE 802.3ba - PMD Type 40GBASE-LR4.